國立中央大學教師履歷平台

期刊著作

• Harnessing Deep Neural Networks for Rapid Knife Wound Identification in Forensic Science: A Proof-of-concept Study
  Sensors and Materials, 37, 5-3, 2115-2133, 2025-01-01
  [ crime scene investigations,deep learning,field programmable gate array,forensic science,knife mark ]

• Aging-Aware Energy-Efficient Task Deployment of Heterogeneous Multicore Systems
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 43, 5, 1580-1593, 2024-05-01
  [ Aging degradation,asymmetric aging,energy,heterogeneous multicore system,lifetime,negative bias temperature instability (NBTI),reliability ]

• DRC Violation Prediction After Global Route Through Convolutional Neural Network
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 31, 9, 1425-1438, 2023-09-01
  [ Design rule checking (DRC),neural networks,physical design (EDA),physical verification,supervised learning by classification ]

• An efficient NBTI-aware wake-up strategy: Concept, design, and manipulation
  Integration, the VLSI Journal, 80, 60-71, 2021-09-01
  [ NBTI effect,Power gating,Sleep transistor,Wake-up sequence,Wake-up strategy ]

• Energy-Efficient Monolithic 3-D SRAM Cell with BEOL MoS2FETs for SoC Scaling
  IEEE Transactions on Electron Devices, 67, 10, 4216-4221, 2020-10-01
  [ 2-D material,area efficiency,back-end-of-The-line (BEOL),energy efficiency,monolithic 3-D (M3D) integration,SRAM ]

• Novel Spare TSV Deployment for 3-D ICs Considering Yield and Timing Constraints
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 34, 4, 577-588, 2015-04-01
  [ Fault-tolerance,reliability,three dimensional integrated circuits (3-D IC),through silicon via (TSV) ]

• Multibit retention registers for power gated designs: Concept, design, and deployment
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 33, 4, 507-518, 2014-01-01
  [ Low power,mode transition latency,multibit retention register,power gating ]

研討會著作

• Overcoming Training Data Scarcity in Routing Demand Prediction via Ensemble Learning
  681-688, 2025-06-29
  [ Ensemble learning,Feature importance,Placement features,Routing demand prediction,XGBoost ]

• Optimizing Reliability and Energy Efficiency in Heterogeneous Multicore Systems: A Novel Task Deployment Strategy
  126-133, 2025-06-29
  [ aging effects,DVFS,Heterogeneous multicore system,lifetime extension,reliability,task replication,transient error ]

• BASIS SHARING: CROSS-LAYER PARAMETER SHARING FOR LARGE LANGUAGE MODEL COMPRESSION
  39540-39558, 2025-01-01
  

• FastGDBN: A GPU-Accelerated DNN for Identifying Good Dies in Bad Neighborhoods
  2025-01-01
  [ GDBC,GDBN,Outlier detection,Wafer map ]

• CORA: Improving Computational Throughput in Compressor-Based MAC Designs via Carry-Out Replaced Multiply-Accumulator
  2025-01-01
  [ compressor-based MAC,critical path,high speed,low-power,throughput ]

• CIM for Transformer Models: Enhancing Large Language Model Inference Efficiency
  2025-01-01
  

• GNN-Based INC and IVC Co-Optimization for Aging Mitigation
  2024-01-01
  [ aging mitigation,gate replacement,Graph Neural Network (GNN),Input Vector Control (IVC),Internal Node Control (INC),lifetime enhancement,Negative Bias Temperature Instability (NBTI) ]

• Enhancing Stability in CRPs: A Novel Parallel Scan-Chain PUF Design Considering Aging Effects
  2024-01-01
  [ aging,ECC,Parallel scan-chain PUF,PUF ]

• Using Deep Neural Networks Analyzing Wound Images for Forensic Tool Mark Identification
  479-480, 2024-01-01
  [ Deep neural network,Forensic science,FPGA,Wound identification ]

• Exploring a Hybrid SRAM-RRAM Computing-In-Memory Architecture for DNNs Model Inference
  112-117, 2024-01-01
  [ Computing-In-Memory (CIM),DNNs,RRAM,SRAM,von Neumann architectures ]

• Aging Mitigation in Systolic Array Accelerators: Balancing PE Loads for Enhanced Reliability
  2024-01-01
  [ AI accelerator,data mapping,fission,HCI,NBTI,Systolic array ]

• Special Session: Overcoming Transient Faults and Aging Effects in Digital Computing-in-Memory Architectures: Detection, Tolerance, and Mitigation Strategies
  2024-01-01
  [ circuit aging,Computing-in-memory,transient fault ]

• IR-drop and Routing Congestion Aware PDN Refinement Framework for Timing Optimization
  133-134, 2024-01-01
  [ cost function,ID-drop,PDN Refinement,Routing Congestion,Timing Optimization ]

• CARDS: A Novel Detailed Macro Placement Framework for Minimizing Wirelength
  131-132, 2024-01-01
  [ Binary search tree,Detailed macroplacement,Macro flipping,Macro movement,Wirelength minimization ]

• TNSS:Two-Nibble Sparsity-Aware Stride-Decomposing Acceleration for Convolutional Neural Networks
  795-799, 2024-01-01
  [ bit-level sparsity,convolution neural networks,data compression,data-level sparsity,stride-decompose ]

• DRC Violation Prediction with Pre-global-routing Features Through Convolutional Neural Network
  313-319, 2023-06-05
  [ cnn,drv prediction,pre-global-routing features,under-sampling ]

• An On-Line Aging Detection and Tolerance Framework for Improving Reliability of STT-MRAMs
  13-18, 2023-01-16
  [ aging detection mechanism,aging tolerance mechanism,reliability enhancement,STT-MRAM,TDDB ]

• Reliability of Computing-In-Memories: Threats, Detection Methods, and Mitigation Approaches
  2023-01-01
  [ Circuit Aging,Computing-in-memory,Reliability ]

• DOC: A Novel DOuble-Contour-Based Macro Placement Framework for Mixed-Size Designs
  1392-1397, 2023-01-01
  

• Invited Paper: Overview of 2023 CAD Contest at ICCAD
  2023-01-01
  [ 3D-IC,CAD Contest,circuit verification,computer-aided design,electronic design automation,hardware security,ML for EDA ]

• Overview of 2022 CAD contest at ICCAD
  2022-10-30
  [ 3D-IC,CAD Contest,circuit security,computer-aided design,design space exploration,electronic design automation,integrated circuits ]

• A Novel DNN Accelerator for Light-weight Neural Networks: Concept and Design
  250-253, 2022-01-01
  [ CNN Accelerators,Edge AI,light-weight neural networks,MobileNet,ShuffleNet ]

• An Aging Detection and Tolerance Framework for 8T SRAM Dot Product CIM Engine
  161-162, 2022-01-01
  [ 8T SRAM,Aging,Computing In-Memory,DVS ]

• A novel nbti-aware chip remaining lifetime prediction framework using machine learning
  476-481, 2021-04-07
  

• A Reconfigurable Accelerator Design for Quantized Depthwise Separable Convolutions
  290-291, 2021-01-01
  [ AI accelerator,Mobilenets,Reconfigurable Structure ]

• A Hierarchical and Reconfigurable Process Element Design for Quantized Neural Networks
  278-283, 2021-01-01
  [ Processing Element (PE),Quantized Neural Networks (QNN),Reconfigurable Design ]

• An Aging-Aware CMOS SRAM Structure Design for Boolean Logic In-Memory Computing
  2021-01-01
  [ 8T SRAM,In-Memory Computing,PBTI,supplemental transistor ]

• Overview of 2021 CAD Contest at ICCAD
  2021-01-01
  [ CAD Contest,Computer-aided design,Electronic design automation,Integrated circuits ]

• Power Distribution Network Generation for Optimizing IR-Drop Aware Timing
  2020-11-02
  

• An Artificial Neuron Network Based Chip Health Assessment Framework for IC Recycling
  2020-09-28
  

• Selective sensor placement for cost-effective online aging monitoring and resilience
  95-102, 2020-09-20
  [ Aging monitoring/resilience,Sensor placement,Transition detector ]

• An NBTI-Aware Task Parallelism Scheme for Improving Lifespan of Multi-core Systems
  117-122, 2020-03-01
  [ multi-core system,NBTI,parallel execution,task-To-core mapping ]

• ROAD: Improving reliability of multi-core system via asymmetric aging
  2019-11-01
  

• Exploration and Exploitation of Dual Timing Margins for Improving Power Efficiency of Variable-Latency Designs
  218-223, 2019-07-01
  [ Power Efficiency,Variable latency design ]

• NBTI-aware digital LDO design for edge devices in IoT systems
  2019-03-01
  [ Digital LDO,NBTI effect,Power integrity ]

• An efficient NBTI-aware wake-up strategy for power-gated designs
  901-904, 2018-04-19
  [ NBTI,Power gating,Wake-up sequence ]

• Pattern based runtime voltage emergency prediction: An instruction-aware block sparse compressed sensing approach
  543-548, 2017-02-16
  

• A novel low-cost dynamic logic reconfigurable structure strategy for low power optimization
  250-255, 2016-03-07
  

• Q-learning based dynamic voltage scaling for designs with graceful degradation
  41-48, 2015-03-29
  [ Dynamic voltage scaling,Graceful degradation,Q-learning ]

• Critical path monitor enabled dynamic voltage scaling for graceful degradation in sub-threshold designs
  2014-01-01
  

• Yield and timing constrained spare TSV assignment for three-dimensional integrated circuits
  2014-01-01
  [ 3D IC,Fault-Tolerance,Reliability,TSV ]

• Efficient multiple-bit retention register assignment for power gated design: Concept and algorithms
  309-316, 2012-12-01
  [ Low power,power gating,retention register ]

• Efficient on-line module-level wake-up scheduling for high performance multi-module designs
  97-103, 2012-05-01
  [ Module-level,Power gating,System-level,Wakeup scheduling ]

• NBTI-aware power gating design
  609-614, 2011-03-28
  

專書

• Physical Design for 3D Integrated Circuits
  193-227, 2017-01-01