國立中央大學教師履歷平台

教師個人簡歷

中文姓名

陳聿廣

英文姓名

Chen,Yu-Guang

電子郵件

andyygchen@ee.ncu.edu.tw

Integrated Circuit 積體電路 power gating reliability asymmetric aging IC NBTI 機器學習 PDN Power Distribution Network Low power IC Design and Optimization Reliable In-Memory Computing 低功耗晶片設計最佳化記憶體內運算晶片老化緩解與可靠晶片設計電子設計自動化 IMC AI for EDA AI於EDA之應用 Circuit Aging Mitigation and Tolerance Design and Optimization Electronic Design Automation

現職	國立中央大學資訊電機學院電機工程學系副教授
專長	電子設計自動化晶片老化緩解與可靠晶片設計低功耗晶片設計最佳化記憶體內運算(IMC) AI於EDA之應用 Electronic Design Automation Circuit Aging Mitigation and Tolerance Low power IC Design and Optimization Reliable In-Memory Computing Power Distribution Network (PDN) Design and Optimization AI for EDA
專長簡述
最高學歷	國立清華大學資訊工程學系博士
相關連結	個人網頁 GRB資訊系統

科技部學門領域	E - 工程及應用科學 E14 - 微電子工程 E1414 - 積體電路及系統設計
政府GRB研究專長領域	2 - 工 22 - 電子電機工程
教育部學門領域	5 - 工程、製造及營造 52 - 工程學門 5201 - 電資工程學類

其他補助

運用於電子設計自動化之機器學習精要
1140401~1150331
[計算複雜度,積體電路,設計空間探索 , computational complexity,Integrated Circuit,Design Space Exploration]
智慧晶片系統與應用人才培育計畫-電腦輔助超大型積體電路設計
1130801~1140731
[積體電路,IC設計流程,電腦輔助設計軟體 , Integrated Circuit,IC Design Flow,Computer-Aided Design]
智慧晶片系統與應用人才培育計畫-電腦輔助超大型積體電路設計
1120801~1130731
[積體電路,人工智慧,機器學習 , Integrated Circuit,AI,ML]
智慧晶片系統與應用跨校教學聯盟計畫-模組教材發展計畫-晶片及硬體之供應鏈層次的資安防護設計
1110401~1120331
[IC及IP安全防護 , IC/IP Protections]
智慧晶片系統與應用跨校教學聯盟計畫-模組教材發展計畫-晶片及硬體之供應鏈層次的資安防護設計
1100701~1110331
[IC及IP安全防護 , IC/IP Protections]

高教深耕計畫

113年以實踐研究為導向之教學創新推動計畫-陳聿廣老師
1130101~1131220
適用於電機專業的程式設計翻轉教材設計及開發
1120101~1121231
多功能程式自動評量系統開發精進及適用電機專業的程式設計實驗模組開發計畫(7月30日關帳)
1120101~1120730
多功能程式自動評量系統開發精進及適用電機專業的程式設計實驗模組開發計畫
1110801~1111231
電腦輔助超大型積體電路設計之程式實作能力數位教材開發與精進計畫
1110101~1110731
電腦輔助超大型積體電路設計程式實作能力改善計畫
1100301~1100731
計算機概論 I線上課程製作及程式自動評量系統建置計畫
1100101~1101231
[程式碼檢視 , code review]

國科會計畫統計

運算記憶體之測試與可靠性增強技術-子計畫三：運算記憶體之老化偵測、緩解策略與自動化技術
1140801~1150731
運算記憶體之測試與可靠性增強技術-子計畫三：運算記憶體之老化偵測、緩解策略與自動化技術
1130801~1140731
運算記憶體之測試與可靠性增強技術-子計畫三：運算記憶體之老化偵測、緩解策略與自動化技術
1120801~1130731
考量老化現象之低功耗設計可靠度分析及優化策略
1090101~1091031
[電源閘控,喚醒排程,負偏壓溫度不穩定效應,晶片健康狀況,機器學習 , power gating,wake-up scheduling,NBTI,chip health,machine learning]
考量老化現象之低功耗設計可靠度分析及優化策略
1080101~1081231
[電源閘控,喚醒排程,負偏壓溫度不穩定效應,晶片健康狀況,機器學習 , power gating,wake-up scheduling,NBTI,chip health,machine learning]
考量老化現象之低功耗設計可靠度分析及優化策略
1070101~1071231
[電源閘控,喚醒排程,負偏壓溫度不穩定效應,晶片健康狀況,機器學習 , power gating,wake-up scheduling,NBTI,chip health,machine learning]

期刊著作

Harnessing Deep Neural Networks for Rapid Knife Wound Identification in Forensic Science: A Proof-of-concept Study
Sensors and Materials, 37, 5-3, 2115-2133, 2025-01-01
[ crime scene investigations,deep learning,field programmable gate array,forensic science,knife mark ]
Aging-Aware Energy-Efficient Task Deployment of Heterogeneous Multicore Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 43, 5, 1580-1593, 2024-05-01
[ Aging degradation,asymmetric aging,energy,heterogeneous multicore system,lifetime,negative bias temperature instability (NBTI),reliability ]
DRC Violation Prediction After Global Route Through Convolutional Neural Network
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 31, 9, 1425-1438, 2023-09-01
[ Design rule checking (DRC),neural networks,physical design (EDA),physical verification,supervised learning by classification ]
An efficient NBTI-aware wake-up strategy: Concept, design, and manipulation
Integration, the VLSI Journal, 80, 60-71, 2021-09-01
[ NBTI effect,Power gating,Sleep transistor,Wake-up sequence,Wake-up strategy ]
Energy-Efficient Monolithic 3-D SRAM Cell with BEOL MoS2FETs for SoC Scaling
IEEE Transactions on Electron Devices, 67, 10, 4216-4221, 2020-10-01
[ 2-D material,area efficiency,back-end-of-The-line (BEOL),energy efficiency,monolithic 3-D (M3D) integration,SRAM ]
Novel Spare TSV Deployment for 3-D ICs Considering Yield and Timing Constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 34, 4, 577-588, 2015-04-01
[ Fault-tolerance,reliability,three dimensional integrated circuits (3-D IC),through silicon via (TSV) ]
Multibit retention registers for power gated designs: Concept, design, and deployment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 33, 4, 507-518, 2014-01-01
[ Low power,mode transition latency,multibit retention register,power gating ]

研討會著作

BASIS SHARING: CROSS-LAYER PARAMETER SHARING FOR LARGE LANGUAGE MODEL COMPRESSION
39540-39558, 2025-01-01
GNN-Based INC and IVC Co-Optimization for Aging Mitigation
2024-01-01
[ aging mitigation,gate replacement,Graph Neural Network (GNN),Input Vector Control (IVC),Internal Node Control (INC),lifetime enhancement,Negative Bias Temperature Instability (NBTI) ]
Enhancing Stability in CRPs: A Novel Parallel Scan-Chain PUF Design Considering Aging Effects
2024-01-01
[ aging,ECC,Parallel scan-chain PUF,PUF ]
Using Deep Neural Networks Analyzing Wound Images for Forensic Tool Mark Identification
479-480, 2024-01-01
[ Deep neural network,Forensic science,FPGA,Wound identification ]
Exploring a Hybrid SRAM-RRAM Computing-In-Memory Architecture for DNNs Model Inference
112-117, 2024-01-01
[ Computing-In-Memory (CIM),DNNs,RRAM,SRAM,von Neumann architectures ]
Aging Mitigation in Systolic Array Accelerators: Balancing PE Loads for Enhanced Reliability
2024-01-01
[ AI accelerator,data mapping,fission,HCI,NBTI,Systolic array ]
Special Session: Overcoming Transient Faults and Aging Effects in Digital Computing-in-Memory Architectures: Detection, Tolerance, and Mitigation Strategies
2024-01-01
[ circuit aging,Computing-in-memory,transient fault ]
IR-drop and Routing Congestion Aware PDN Refinement Framework for Timing Optimization
133-134, 2024-01-01
[ cost function,ID-drop,PDN Refinement,Routing Congestion,Timing Optimization ]
CARDS: A Novel Detailed Macro Placement Framework for Minimizing Wirelength
131-132, 2024-01-01
[ Binary search tree,Detailed macroplacement,Macro flipping,Macro movement,Wirelength minimization ]
TNSS:Two-Nibble Sparsity-Aware Stride-Decomposing Acceleration for Convolutional Neural Networks
795-799, 2024-01-01
[ bit-level sparsity,convolution neural networks,data compression,data-level sparsity,stride-decompose ]
DRC Violation Prediction with Pre-global-routing Features Through Convolutional Neural Network
313-319, 2023-06-05
[ cnn,drv prediction,pre-global-routing features,under-sampling ]
An On-Line Aging Detection and Tolerance Framework for Improving Reliability of STT-MRAMs
13-18, 2023-01-16
[ aging detection mechanism,aging tolerance mechanism,reliability enhancement,STT-MRAM,TDDB ]
Reliability of Computing-In-Memories: Threats, Detection Methods, and Mitigation Approaches
2023-01-01
[ Circuit Aging,Computing-in-memory,Reliability ]
DOC: A Novel DOuble-Contour-Based Macro Placement Framework for Mixed-Size Designs
1392-1397, 2023-01-01
Invited Paper: Overview of 2023 CAD Contest at ICCAD
2023-01-01
[ 3D-IC,CAD Contest,circuit verification,computer-aided design,electronic design automation,hardware security,ML for EDA ]
Overview of 2022 CAD contest at ICCAD
2022-10-30
[ 3D-IC,CAD Contest,circuit security,computer-aided design,design space exploration,electronic design automation,integrated circuits ]
A Novel DNN Accelerator for Light-weight Neural Networks: Concept and Design
250-253, 2022-01-01
[ CNN Accelerators,Edge AI,light-weight neural networks,MobileNet,ShuffleNet ]
An Aging Detection and Tolerance Framework for 8T SRAM Dot Product CIM Engine
161-162, 2022-01-01
[ 8T SRAM,Aging,Computing In-Memory,DVS ]
A novel nbti-aware chip remaining lifetime prediction framework using machine learning
476-481, 2021-04-07
A Reconfigurable Accelerator Design for Quantized Depthwise Separable Convolutions
290-291, 2021-01-01
[ AI accelerator,Mobilenets,Reconfigurable Structure ]
A Hierarchical and Reconfigurable Process Element Design for Quantized Neural Networks
278-283, 2021-01-01
[ Processing Element (PE),Quantized Neural Networks (QNN),Reconfigurable Design ]
An Aging-Aware CMOS SRAM Structure Design for Boolean Logic In-Memory Computing
2021-01-01
[ 8T SRAM,In-Memory Computing,PBTI,supplemental transistor ]
Overview of 2021 CAD Contest at ICCAD
2021-01-01
[ CAD Contest,Computer-aided design,Electronic design automation,Integrated circuits ]
Power Distribution Network Generation for Optimizing IR-Drop Aware Timing
2020-11-02
An Artificial Neuron Network Based Chip Health Assessment Framework for IC Recycling
2020-09-28
Selective sensor placement for cost-effective online aging monitoring and resilience
95-102, 2020-09-20
[ Aging monitoring/resilience,Sensor placement,Transition detector ]
An NBTI-Aware Task Parallelism Scheme for Improving Lifespan of Multi-core Systems
117-122, 2020-03-01
[ multi-core system,NBTI,parallel execution,task-To-core mapping ]
ROAD: Improving reliability of multi-core system via asymmetric aging
2019-11-01
Exploration and Exploitation of Dual Timing Margins for Improving Power Efficiency of Variable-Latency Designs
218-223, 2019-07-01
[ Power Efficiency,Variable latency design ]
NBTI-aware digital LDO design for edge devices in IoT systems
2019-03-01
[ Digital LDO,NBTI effect,Power integrity ]
An efficient NBTI-aware wake-up strategy for power-gated designs
901-904, 2018-04-19
[ NBTI,Power gating,Wake-up sequence ]
Pattern based runtime voltage emergency prediction: An instruction-aware block sparse compressed sensing approach
543-548, 2017-02-16
A novel low-cost dynamic logic reconfigurable structure strategy for low power optimization
250-255, 2016-03-07
Q-learning based dynamic voltage scaling for designs with graceful degradation
41-48, 2015-03-29
[ Dynamic voltage scaling,Graceful degradation,Q-learning ]
Critical path monitor enabled dynamic voltage scaling for graceful degradation in sub-threshold designs
2014-01-01
Yield and timing constrained spare TSV assignment for three-dimensional integrated circuits
2014-01-01
[ 3D IC,Fault-Tolerance,Reliability,TSV ]
Efficient multiple-bit retention register assignment for power gated design: Concept and algorithms
309-316, 2012-12-01
[ Low power,power gating,retention register ]
Efficient on-line module-level wake-up scheduling for high performance multi-module designs
97-103, 2012-05-01
[ Module-level,Power gating,System-level,Wakeup scheduling ]
NBTI-aware power gating design
609-614, 2011-03-28

專書

Physical Design for 3D Integrated Circuits
193-227, 2017-01-01

其他補助

運用於電子設計自動化之機器學習精要 1140401~1150331 [計算複雜度,積體電路,設計空間探索 , computational complexity,Integrated Circuit,Design Space Exploration]

智慧晶片系統與應用人才培育計畫-電腦輔助超大型積體電路設計 1130801~1140731 [積體電路,IC設計流程,電腦輔助設計軟體 , Integrated Circuit,IC Design Flow,Computer-Aided Design]

智慧晶片系統與應用人才培育計畫-電腦輔助超大型積體電路設計 1120801~1130731 [積體電路,人工智慧,機器學習 , Integrated Circuit,AI,ML]

智慧晶片系統與應用跨校教學聯盟計畫-模組教材發展計畫-晶片及硬體之供應鏈層次的資安防護設計 1110401~1120331 [IC及IP安全防護 , IC/IP Protections]

智慧晶片系統與應用跨校教學聯盟計畫-模組教材發展計畫-晶片及硬體之供應鏈層次的資安防護設計 1100701~1110331 [IC及IP安全防護 , IC/IP Protections]

高教深耕計畫

113年以實踐研究為導向之教學創新推動計畫-陳聿廣老師 1130101~1131220

適用於電機專業的程式設計翻轉教材設計及開發 1120101~1121231

多功能程式自動評量系統開發精進及適用電機專業的程式設計實驗模組開發計畫(7月30日關帳) 1120101~1120730

多功能程式自動評量系統開發精進及適用電機專業的程式設計實驗模組開發計畫 1110801~1111231

電腦輔助超大型積體電路設計之程式實作能力數位教材開發與精進計畫 1110101~1110731

電腦輔助超大型積體電路設計程式實作能力改善計畫 1100301~1100731

計算機概論 I線上課程製作及程式自動評量系統建置計畫 1100101~1101231 [程式碼檢視 , code review]

國科會計畫統計

運算記憶體之測試與可靠性增強技術-子計畫三：運算記憶體之老化偵測、緩解策略與自動化技術 1140801~1150731

運算記憶體之測試與可靠性增強技術-子計畫三：運算記憶體之老化偵測、緩解策略與自動化技術 1130801~1140731

運算記憶體之測試與可靠性增強技術-子計畫三：運算記憶體之老化偵測、緩解策略與自動化技術 1120801~1130731

考量老化現象之低功耗設計可靠度分析及優化策略 1090101~1091031 [電源閘控,喚醒排程,負偏壓溫度不穩定效應,晶片健康狀況,機器學習 , power gating,wake-up scheduling,NBTI,chip health,machine learning]

考量老化現象之低功耗設計可靠度分析及優化策略 1080101~1081231 [電源閘控,喚醒排程,負偏壓溫度不穩定效應,晶片健康狀況,機器學習 , power gating,wake-up scheduling,NBTI,chip health,machine learning]

考量老化現象之低功耗設計可靠度分析及優化策略 1070101~1071231 [電源閘控,喚醒排程,負偏壓溫度不穩定效應,晶片健康狀況,機器學習 , power gating,wake-up scheduling,NBTI,chip health,machine learning]

期刊著作

Harnessing Deep Neural Networks for Rapid Knife Wound Identification in Forensic Science: A Proof-of-concept Study Sensors and Materials, 37, 5-3, 2115-2133, 2025-01-01 [ crime scene investigations,deep learning,field programmable gate array,forensic science,knife mark ]

An efficient NBTI-aware wake-up strategy: Concept, design, and manipulation Integration, the VLSI Journal, 80, 60-71, 2021-09-01 [ NBTI effect,Power gating,Sleep transistor,Wake-up sequence,Wake-up strategy ]

Energy-Efficient Monolithic 3-D SRAM Cell with BEOL MoS2FETs for SoC Scaling IEEE Transactions on Electron Devices, 67, 10, 4216-4221, 2020-10-01 [ 2-D material,area efficiency,back-end-of-The-line (BEOL),energy efficiency,monolithic 3-D (M3D) integration,SRAM ]

Novel Spare TSV Deployment for 3-D ICs Considering Yield and Timing Constraints IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 34, 4, 577-588, 2015-04-01 [ Fault-tolerance,reliability,three dimensional integrated circuits (3-D IC),through silicon via (TSV) ]

Multibit retention registers for power gated designs: Concept, design, and deployment IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 33, 4, 507-518, 2014-01-01 [ Low power,mode transition latency,multibit retention register,power gating ]

研討會著作

BASIS SHARING: CROSS-LAYER PARAMETER SHARING FOR LARGE LANGUAGE MODEL COMPRESSION 39540-39558, 2025-01-01

GNN-Based INC and IVC Co-Optimization for Aging Mitigation 2024-01-01 [ aging mitigation,gate replacement,Graph Neural Network (GNN),Input Vector Control (IVC),Internal Node Control (INC),lifetime enhancement,Negative Bias Temperature Instability (NBTI) ]

Enhancing Stability in CRPs: A Novel Parallel Scan-Chain PUF Design Considering Aging Effects 2024-01-01 [ aging,ECC,Parallel scan-chain PUF,PUF ]

Using Deep Neural Networks Analyzing Wound Images for Forensic Tool Mark Identification 479-480, 2024-01-01 [ Deep neural network,Forensic science,FPGA,Wound identification ]

Exploring a Hybrid SRAM-RRAM Computing-In-Memory Architecture for DNNs Model Inference 112-117, 2024-01-01 [ Computing-In-Memory (CIM),DNNs,RRAM,SRAM,von Neumann architectures ]

Aging Mitigation in Systolic Array Accelerators: Balancing PE Loads for Enhanced Reliability 2024-01-01 [ AI accelerator,data mapping,fission,HCI,NBTI,Systolic array ]

Special Session: Overcoming Transient Faults and Aging Effects in Digital Computing-in-Memory Architectures: Detection, Tolerance, and Mitigation Strategies 2024-01-01 [ circuit aging,Computing-in-memory,transient fault ]

IR-drop and Routing Congestion Aware PDN Refinement Framework for Timing Optimization 133-134, 2024-01-01 [ cost function,ID-drop,PDN Refinement,Routing Congestion,Timing Optimization ]

CARDS: A Novel Detailed Macro Placement Framework for Minimizing Wirelength 131-132, 2024-01-01 [ Binary search tree,Detailed macroplacement,Macro flipping,Macro movement,Wirelength minimization ]

TNSS:Two-Nibble Sparsity-Aware Stride-Decomposing Acceleration for Convolutional Neural Networks 795-799, 2024-01-01 [ bit-level sparsity,convolution neural networks,data compression,data-level sparsity,stride-decompose ]

DRC Violation Prediction with Pre-global-routing Features Through Convolutional Neural Network 313-319, 2023-06-05 [ cnn,drv prediction,pre-global-routing features,under-sampling ]

An On-Line Aging Detection and Tolerance Framework for Improving Reliability of STT-MRAMs 13-18, 2023-01-16 [ aging detection mechanism,aging tolerance mechanism,reliability enhancement,STT-MRAM,TDDB ]

Reliability of Computing-In-Memories: Threats, Detection Methods, and Mitigation Approaches 2023-01-01 [ Circuit Aging,Computing-in-memory,Reliability ]

DOC: A Novel DOuble-Contour-Based Macro Placement Framework for Mixed-Size Designs 1392-1397, 2023-01-01

Invited Paper: Overview of 2023 CAD Contest at ICCAD 2023-01-01 [ 3D-IC,CAD Contest,circuit verification,computer-aided design,electronic design automation,hardware security,ML for EDA ]

Overview of 2022 CAD contest at ICCAD 2022-10-30 [ 3D-IC,CAD Contest,circuit security,computer-aided design,design space exploration,electronic design automation,integrated circuits ]

A Novel DNN Accelerator for Light-weight Neural Networks: Concept and Design 250-253, 2022-01-01 [ CNN Accelerators,Edge AI,light-weight neural networks,MobileNet,ShuffleNet ]

An Aging Detection and Tolerance Framework for 8T SRAM Dot Product CIM Engine 161-162, 2022-01-01 [ 8T SRAM,Aging,Computing In-Memory,DVS ]

A novel nbti-aware chip remaining lifetime prediction framework using machine learning 476-481, 2021-04-07

A Reconfigurable Accelerator Design for Quantized Depthwise Separable Convolutions 290-291, 2021-01-01 [ AI accelerator,Mobilenets,Reconfigurable Structure ]

A Hierarchical and Reconfigurable Process Element Design for Quantized Neural Networks 278-283, 2021-01-01 [ Processing Element (PE),Quantized Neural Networks (QNN),Reconfigurable Design ]

An Aging-Aware CMOS SRAM Structure Design for Boolean Logic In-Memory Computing 2021-01-01 [ 8T SRAM,In-Memory Computing,PBTI,supplemental transistor ]

Overview of 2021 CAD Contest at ICCAD 2021-01-01 [ CAD Contest,Computer-aided design,Electronic design automation,Integrated circuits ]

Power Distribution Network Generation for Optimizing IR-Drop Aware Timing 2020-11-02

An Artificial Neuron Network Based Chip Health Assessment Framework for IC Recycling 2020-09-28

Selective sensor placement for cost-effective online aging monitoring and resilience 95-102, 2020-09-20 [ Aging monitoring/resilience,Sensor placement,Transition detector ]

An NBTI-Aware Task Parallelism Scheme for Improving Lifespan of Multi-core Systems 117-122, 2020-03-01 [ multi-core system,NBTI,parallel execution,task-To-core mapping ]

ROAD: Improving reliability of multi-core system via asymmetric aging 2019-11-01

Exploration and Exploitation of Dual Timing Margins for Improving Power Efficiency of Variable-Latency Designs 218-223, 2019-07-01 [ Power Efficiency,Variable latency design ]

NBTI-aware digital LDO design for edge devices in IoT systems 2019-03-01 [ Digital LDO,NBTI effect,Power integrity ]

An efficient NBTI-aware wake-up strategy for power-gated designs 901-904, 2018-04-19 [ NBTI,Power gating,Wake-up sequence ]

Pattern based runtime voltage emergency prediction: An instruction-aware block sparse compressed sensing approach 543-548, 2017-02-16

A novel low-cost dynamic logic reconfigurable structure strategy for low power optimization 250-255, 2016-03-07

Q-learning based dynamic voltage scaling for designs with graceful degradation 41-48, 2015-03-29 [ Dynamic voltage scaling,Graceful degradation,Q-learning ]

Critical path monitor enabled dynamic voltage scaling for graceful degradation in sub-threshold designs 2014-01-01

Yield and timing constrained spare TSV assignment for three-dimensional integrated circuits 2014-01-01 [ 3D IC,Fault-Tolerance,Reliability,TSV ]

Efficient multiple-bit retention register assignment for power gated design: Concept and algorithms 309-316, 2012-12-01 [ Low power,power gating,retention register ]

Efficient on-line module-level wake-up scheduling for high performance multi-module designs 97-103, 2012-05-01 [ Module-level,Power gating,System-level,Wakeup scheduling ]

NBTI-aware power gating design 609-614, 2011-03-28

專書

Physical Design for 3D Integrated Circuits 193-227, 2017-01-01

運用於電子設計自動化之機器學習精要
1140401~1150331
[計算複雜度,積體電路,設計空間探索 , computational complexity,Integrated Circuit,Design Space Exploration]

智慧晶片系統與應用人才培育計畫-電腦輔助超大型積體電路設計
1130801~1140731
[積體電路,IC設計流程,電腦輔助設計軟體 , Integrated Circuit,IC Design Flow,Computer-Aided Design]

智慧晶片系統與應用人才培育計畫-電腦輔助超大型積體電路設計
1120801~1130731
[積體電路,人工智慧,機器學習 , Integrated Circuit,AI,ML]

智慧晶片系統與應用跨校教學聯盟計畫-模組教材發展計畫-晶片及硬體之供應鏈層次的資安防護設計
1110401~1120331
[IC及IP安全防護 , IC/IP Protections]

智慧晶片系統與應用跨校教學聯盟計畫-模組教材發展計畫-晶片及硬體之供應鏈層次的資安防護設計
1100701~1110331
[IC及IP安全防護 , IC/IP Protections]

113年以實踐研究為導向之教學創新推動計畫-陳聿廣老師
1130101~1131220

適用於電機專業的程式設計翻轉教材設計及開發
1120101~1121231

多功能程式自動評量系統開發精進及適用電機專業的程式設計實驗模組開發計畫(7月30日關帳)
1120101~1120730

多功能程式自動評量系統開發精進及適用電機專業的程式設計實驗模組開發計畫
1110801~1111231

電腦輔助超大型積體電路設計之程式實作能力數位教材開發與精進計畫
1110101~1110731

電腦輔助超大型積體電路設計程式實作能力改善計畫
1100301~1100731

計算機概論 I線上課程製作及程式自動評量系統建置計畫
1100101~1101231
[程式碼檢視 , code review]

運算記憶體之測試與可靠性增強技術-子計畫三：運算記憶體之老化偵測、緩解策略與自動化技術
1140801~1150731

運算記憶體之測試與可靠性增強技術-子計畫三：運算記憶體之老化偵測、緩解策略與自動化技術
1130801~1140731

運算記憶體之測試與可靠性增強技術-子計畫三：運算記憶體之老化偵測、緩解策略與自動化技術
1120801~1130731

考量老化現象之低功耗設計可靠度分析及優化策略
1090101~1091031
[電源閘控,喚醒排程,負偏壓溫度不穩定效應,晶片健康狀況,機器學習 , power gating,wake-up scheduling,NBTI,chip health,machine learning]

考量老化現象之低功耗設計可靠度分析及優化策略
1080101~1081231
[電源閘控,喚醒排程,負偏壓溫度不穩定效應,晶片健康狀況,機器學習 , power gating,wake-up scheduling,NBTI,chip health,machine learning]

考量老化現象之低功耗設計可靠度分析及優化策略
1070101~1071231
[電源閘控,喚醒排程,負偏壓溫度不穩定效應,晶片健康狀況,機器學習 , power gating,wake-up scheduling,NBTI,chip health,machine learning]

Harnessing Deep Neural Networks for Rapid Knife Wound Identification in Forensic Science: A Proof-of-concept Study
Sensors and Materials, 37, 5-3, 2115-2133, 2025-01-01
[ crime scene investigations,deep learning,field programmable gate array,forensic science,knife mark ]

An efficient NBTI-aware wake-up strategy: Concept, design, and manipulation
Integration, the VLSI Journal, 80, 60-71, 2021-09-01
[ NBTI effect,Power gating,Sleep transistor,Wake-up sequence,Wake-up strategy ]

Energy-Efficient Monolithic 3-D SRAM Cell with BEOL MoS2FETs for SoC Scaling
IEEE Transactions on Electron Devices, 67, 10, 4216-4221, 2020-10-01
[ 2-D material,area efficiency,back-end-of-The-line (BEOL),energy efficiency,monolithic 3-D (M3D) integration,SRAM ]

Novel Spare TSV Deployment for 3-D ICs Considering Yield and Timing Constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 34, 4, 577-588, 2015-04-01
[ Fault-tolerance,reliability,three dimensional integrated circuits (3-D IC),through silicon via (TSV) ]

Multibit retention registers for power gated designs: Concept, design, and deployment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 33, 4, 507-518, 2014-01-01
[ Low power,mode transition latency,multibit retention register,power gating ]

BASIS SHARING: CROSS-LAYER PARAMETER SHARING FOR LARGE LANGUAGE MODEL COMPRESSION
39540-39558, 2025-01-01

GNN-Based INC and IVC Co-Optimization for Aging Mitigation
2024-01-01
[ aging mitigation,gate replacement,Graph Neural Network (GNN),Input Vector Control (IVC),Internal Node Control (INC),lifetime enhancement,Negative Bias Temperature Instability (NBTI) ]

Enhancing Stability in CRPs: A Novel Parallel Scan-Chain PUF Design Considering Aging Effects
2024-01-01
[ aging,ECC,Parallel scan-chain PUF,PUF ]

Using Deep Neural Networks Analyzing Wound Images for Forensic Tool Mark Identification
479-480, 2024-01-01
[ Deep neural network,Forensic science,FPGA,Wound identification ]

Exploring a Hybrid SRAM-RRAM Computing-In-Memory Architecture for DNNs Model Inference
112-117, 2024-01-01
[ Computing-In-Memory (CIM),DNNs,RRAM,SRAM,von Neumann architectures ]

Aging Mitigation in Systolic Array Accelerators: Balancing PE Loads for Enhanced Reliability
2024-01-01
[ AI accelerator,data mapping,fission,HCI,NBTI,Systolic array ]

Special Session: Overcoming Transient Faults and Aging Effects in Digital Computing-in-Memory Architectures: Detection, Tolerance, and Mitigation Strategies
2024-01-01
[ circuit aging,Computing-in-memory,transient fault ]

IR-drop and Routing Congestion Aware PDN Refinement Framework for Timing Optimization
133-134, 2024-01-01
[ cost function,ID-drop,PDN Refinement,Routing Congestion,Timing Optimization ]

CARDS: A Novel Detailed Macro Placement Framework for Minimizing Wirelength
131-132, 2024-01-01
[ Binary search tree,Detailed macroplacement,Macro flipping,Macro movement,Wirelength minimization ]

TNSS:Two-Nibble Sparsity-Aware Stride-Decomposing Acceleration for Convolutional Neural Networks
795-799, 2024-01-01
[ bit-level sparsity,convolution neural networks,data compression,data-level sparsity,stride-decompose ]

DRC Violation Prediction with Pre-global-routing Features Through Convolutional Neural Network
313-319, 2023-06-05
[ cnn,drv prediction,pre-global-routing features,under-sampling ]

An On-Line Aging Detection and Tolerance Framework for Improving Reliability of STT-MRAMs
13-18, 2023-01-16
[ aging detection mechanism,aging tolerance mechanism,reliability enhancement,STT-MRAM,TDDB ]

Reliability of Computing-In-Memories: Threats, Detection Methods, and Mitigation Approaches
2023-01-01
[ Circuit Aging,Computing-in-memory,Reliability ]

DOC: A Novel DOuble-Contour-Based Macro Placement Framework for Mixed-Size Designs
1392-1397, 2023-01-01

Invited Paper: Overview of 2023 CAD Contest at ICCAD
2023-01-01
[ 3D-IC,CAD Contest,circuit verification,computer-aided design,electronic design automation,hardware security,ML for EDA ]

Overview of 2022 CAD contest at ICCAD
2022-10-30
[ 3D-IC,CAD Contest,circuit security,computer-aided design,design space exploration,electronic design automation,integrated circuits ]

A Novel DNN Accelerator for Light-weight Neural Networks: Concept and Design
250-253, 2022-01-01
[ CNN Accelerators,Edge AI,light-weight neural networks,MobileNet,ShuffleNet ]

An Aging Detection and Tolerance Framework for 8T SRAM Dot Product CIM Engine
161-162, 2022-01-01
[ 8T SRAM,Aging,Computing In-Memory,DVS ]

A novel nbti-aware chip remaining lifetime prediction framework using machine learning
476-481, 2021-04-07

A Reconfigurable Accelerator Design for Quantized Depthwise Separable Convolutions
290-291, 2021-01-01
[ AI accelerator,Mobilenets,Reconfigurable Structure ]

A Hierarchical and Reconfigurable Process Element Design for Quantized Neural Networks
278-283, 2021-01-01
[ Processing Element (PE),Quantized Neural Networks (QNN),Reconfigurable Design ]

An Aging-Aware CMOS SRAM Structure Design for Boolean Logic In-Memory Computing
2021-01-01
[ 8T SRAM,In-Memory Computing,PBTI,supplemental transistor ]

Overview of 2021 CAD Contest at ICCAD
2021-01-01
[ CAD Contest,Computer-aided design,Electronic design automation,Integrated circuits ]

Power Distribution Network Generation for Optimizing IR-Drop Aware Timing
2020-11-02

An Artificial Neuron Network Based Chip Health Assessment Framework for IC Recycling
2020-09-28

Selective sensor placement for cost-effective online aging monitoring and resilience
95-102, 2020-09-20
[ Aging monitoring/resilience,Sensor placement,Transition detector ]

An NBTI-Aware Task Parallelism Scheme for Improving Lifespan of Multi-core Systems
117-122, 2020-03-01
[ multi-core system,NBTI,parallel execution,task-To-core mapping ]

ROAD: Improving reliability of multi-core system via asymmetric aging
2019-11-01

Exploration and Exploitation of Dual Timing Margins for Improving Power Efficiency of Variable-Latency Designs
218-223, 2019-07-01
[ Power Efficiency,Variable latency design ]

NBTI-aware digital LDO design for edge devices in IoT systems
2019-03-01
[ Digital LDO,NBTI effect,Power integrity ]

An efficient NBTI-aware wake-up strategy for power-gated designs
901-904, 2018-04-19
[ NBTI,Power gating,Wake-up sequence ]

Pattern based runtime voltage emergency prediction: An instruction-aware block sparse compressed sensing approach
543-548, 2017-02-16

A novel low-cost dynamic logic reconfigurable structure strategy for low power optimization
250-255, 2016-03-07

Q-learning based dynamic voltage scaling for designs with graceful degradation
41-48, 2015-03-29
[ Dynamic voltage scaling,Graceful degradation,Q-learning ]

Critical path monitor enabled dynamic voltage scaling for graceful degradation in sub-threshold designs
2014-01-01

Yield and timing constrained spare TSV assignment for three-dimensional integrated circuits
2014-01-01
[ 3D IC,Fault-Tolerance,Reliability,TSV ]

Efficient multiple-bit retention register assignment for power gated design: Concept and algorithms
309-316, 2012-12-01
[ Low power,power gating,retention register ]

Efficient on-line module-level wake-up scheduling for high performance multi-module designs
97-103, 2012-05-01
[ Module-level,Power gating,System-level,Wakeup scheduling ]

NBTI-aware power gating design
609-614, 2011-03-28

Physical Design for 3D Integrated Circuits
193-227, 2017-01-01