教師個人簡歷
現職
國立中央大學
資訊電機學院電機工程學系
教授
專長
人工智慧物聯網電路與系統設計
記憶體內運算
三維積體電路及SOC設計與測試
記憶體設計與測試
專長簡述
Near-Data Processing/物聯網/深度學習
最高學歷
國立清華大學
電機工程學系
博士
科技部學門領域
政府GRB研究專長領域
教育部學門領域
國科會計畫統計
-
運算記憶體之測試與可靠性增強技術-總計畫暨子計畫一:運算記憶體之測試策略與自動化技術
1140801~1150731
-
數位運算記憶體設計與測試自動化(2/5)
1140501~1150430
-
運算記憶體之測試與可靠性增強技術-總計畫暨子計畫一:運算記憶體之測試策略與自動化技術
1130801~1140731
-
運算記憶體之測試與可靠性增強技術-總計畫暨子計畫一:運算記憶體之測試策略與自動化技術
1120801~1130731
-
應用於人體姿勢辨識與機器人之可重組深度神經網路引擎-總計畫暨子計畫一: 應用於監督式學習之可重組深度神經網路技術(1/3)
1100801~1110731
[人工智慧,深度神經網路,監督式學習,強化式學習,可重組,姿勢辨識,機器人 , Artificial Intelligence,Deep Neural Network,Supervised Learning,Reinforcement Learning,Reconfigurable,posture recognition,robotics] -
深度神經網路系統之強健性與可靠性增強技術
1100801~1110731
[深度神經網路,加速器,可靠性,容錯,強健性 , Deep neural network,accelerator,reliability,fault tolerance,robustness] -
高密度高效能半導體之關鍵元件與智慧架構開發(1/2)
1100501~1110731
[混合式AI運算架構,電晶體垂直堆疊,嵌入式磁阻式記憶體,抗變異之記憶體內運算架構 , hybrid AI computing architecture,transistor stacking,monolithic 3D,variation-aware CIM-based NN circuits] -
應用於人體姿勢辨識與機器人之可重組深度神經網路引擎-總計畫暨子計畫一: 應用於監督式學習之可重組深度神經網路技術(1/3)
1090801~1100731
[人工智慧,深度神經網路,監督式學習,強化式學習,可重組,姿勢辨識,機器人 , Artificial Intelligence,Deep Neural Network,Supervised Learning,Reinforcement Learning,Reconfigurable,posture recognition,robotics] -
深度神經網路系統之強健性與可靠性增強技術
1090801~1100731
[深度神經網路,加速器,可靠性,容錯,強健性 , Deep neural network, accelerator, reliability, fault tolerance, robustness] -
重點產業高階人才培訓與就業計畫
1090101~1091231
-
深度神經網路系統之強健性與可靠性增強技術
1080801~1090731
[深度神經網路,加速器,可靠性,容錯,強健性 , Deep neural network, accelerator, reliability, fault tolerance, robustness] -
應用於人體姿勢辨識與機器人之可重組深度神經網路引擎-總計畫暨子計畫一: 應用於監督式學習之可重組深度神經網路技術(1/3)
1080801~1090731
[人工智慧,深度神經網路,監督式學習,強化式學習,可重組,姿勢辨識,機器人 , Artificial Intelligence,Deep Neural Network,Supervised Learning,Reinforcement Learning,Reconfigurable,posture recognition,robotics] -
108年度重點產業高階人才培訓與就業計畫
1080101~1081231
-
應用於物聯網之新興非揮發性記憶體測試技術
1070801~1080731
[物聯網,非揮發性記憶體,電阻式非揮發性記憶體,測試,錯誤模型,測試演算法,自 我測試, , IoT,nonvolatile memory,resistive nonvolatile memory,testing,fault model,test algorithm, built-in self-test,] -
堆疊式記憶體測試與可靠度增強技術
1070801~1080731
[2,5D/3D IC,測試,可靠度,自我測試,自我修復,錯誤更正碼, , 2,5D/3D IC,testing,reliability,built-in self-test,built-in self-repair,error correction code,] -
堆疊式記憶體測試與可靠度增強技術
1060801~1070731
[2,5D/3D IC,測試,可靠度,自我測試,自我修復,錯誤更正碼, , 2,5D/3D IC,testing,reliability,built-in self-test,built-in self-repair,error correction code,] -
應用於物聯網之新興非揮發性記憶體測試技術
1060801~1070731
[物聯網,非揮發性記憶體,電阻式非揮發性記憶體,測試,錯誤模型,測試演算法,自 我測試, , IoT,nonvolatile memory,resistive nonvolatile memory,testing,fault model,test algorithm, built-in self-test,] -
應用於物聯網之新興非揮發性記憶體測試技術
1050801~1060731
[物聯網,非揮發性記憶體,電阻式非揮發性記憶體,測試,錯誤模型,測試演算法,自 我測試, , IoT,nonvolatile memory,resistive nonvolatile memory,testing,fault model,test algorithm, built-in self-test,] -
堆疊式記憶體測試與可靠度增強技術
1050801~1060731
[2,5D/3D IC,測試,可靠度,自我測試,自我修復,錯誤更正碼, , 2,5D/3D IC,testing,reliability,built-in self-test,built-in self-repair,error correction code,] -
應用於三維積體電路可測性及可靠性設計技術-總計畫暨子計畫一:三維積體電路中堆疊式記憶體與晶粒間連接線可測性與可靠性技術
1040501~1050731
[可靠度,測試,三維積體電路,晶粒間導線,堆疊式記憶體 , three-dimensional integrated circuit,inter-die interconnection,stacked memory,testing,reliability]
期刊著作
-
Hardware Trojan Design With Low Overhead and High Destructiveness for STT-MRAM-Based CIMs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 44, 9, 3260-3273, 2025-01-01
[ Hardware security,in-memory computing,integrated circuits,trojan horse,trusted computing ] -
Testing of in-memory-computing memories with 8 T SRAMs
Microelectronics Reliability, 123, 2021-08-01
[ 8 T SRAM,In-memory computing,March test,Static random access memory,Test ] -
Energy-Efficient Monolithic 3-D SRAM Cell with BEOL MoS2FETs for SoC Scaling
IEEE Transactions on Electron Devices, 67, 10, 4216-4221, 2020-10-01
[ 2-D material,area efficiency,back-end-of-The-line (BEOL),energy efficiency,monolithic 3-D (M3D) integration,SRAM ] -
Conference Reports: Report on 2017 IEEE Asian Test Symposium
IEEE Design and Test, 35, 2, 103-104, 2018-04-01 -
High repair-efficiency BISR scheme for RAMs by reusing bitmap for bit redundancy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23, 9, 1720-1728, 2015-09-01
[ Built-in redundancy analyzer (BIRA) , built-in self-repair (BISR) , local bitmap , memory test , random access memories (RAMs) ] -
Hierarchical test integration methodology for 3-D ICs
IEEE Design and Test, 32, 4, 59-70, 2015-07-01 -
A BIST scheme with the ability of diagnostic data compression for RAMs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 33, 12, 2020-2024, 2014-01-01
[ built-in self-test , compression , diagnosis , March test , Random access memory ] -
Testing Disturbance Faults in Various NAND Flash Memories
Journal of Electronic Testing: Theory and Applications (JETTA), 30, 6, 643-652, 2014-01-01
[ Disturbance fault , Flash memory , March test , NAND flash ] -
A self-repair technique for content addressable memories with address-input-free writing function
Journal of Information Science and Engineering, 29, 3, 493-507, 2013-05-01
[ Built-in self-repair , Content addressable memory , Repair , Test , Yield improvement ] -
A built-in self-repair scheme for 3-D RAMs with interdie redundancy
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 32, 4, 572-583, 2013-03-25
[ 3-D integrated circuit (IC) , 3-D random access memory (RAM) , memory repair , memory testing , through-silicon-via (TSV) , yield improvement ] -
Testing and diagnosing comparison faults of TCAMs with asymmetric cells
IEEE Transactions on Computers, 61, 11, 1576-1587, 2012-10-16
[ comparison fault , content addressable memory (CAM) , diagnosis , march test , Memory testing , ternary CAM ] -
Built-in self-repair scheme for the TSVs in 3-D ICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 31, 10, 1600-1613, 2012-09-28
[ 3-D integrated circuit (IC) , built-in self-repair (BISR) , built-in self-test , fuse , through-silicon-via (TSV) ] -
Cost-efficient built-In redundancy analysis with optimal repair rate for RAMs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 31, 6, 930-940, 2012-05-29
[ Built-in redundancy analysis (BIRA) , built-in self-repair (BISR) , built-in self-test , local bitmap , RAMs , redundancy ] -
Low-cost self-test techniques for small RAMs in SOCs using enhanced IEEE 1500 test wrappers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20, 11, 2123-2127, 2012-01-01
[ built-in self-test (BIST) , IEEE 1500 , multi-port RAM , random access memory (RAM) , system-on-chip (SOC) ] -
A low-power ternary content addressable memory with Pai-Sigma matchlines
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20, 10, 1909-1913, 2012-01-01
[ Content addressable memories (CAM) , low power , networking , ternary CAM (TCAM) ] -
A low-cost built-in redundancy-analysis scheme for word-oriented RAMs with 2-D redundancy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 19, 11, 1983-1995, 2011-11-01
[ Built-in redundancy-analysis (BIRA) , built-in self-repair (BISR) , local bitmap , RAMs , redundancy ] -
Memory built-in self-repair planning framework for RAMs in SoCs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 30, 11, 1731-1743, 2011-11-01
[ BISR allocation , built-in self-repair , built-in self-test , RAMs , system-on-chip (SoC) , test scheduling ] -
SETBIST: An soft-error tolerant built-in self-test scheme for random access memories
Journal of Information Science and Engineering, 27, 2, 643-656, 2011-03-01
[ Built-in self-test,Fault-tolerance,Memory test,Random access memories,Reliability ] -
A Built-in Method to Repair SoC RAMs in Parallel
IEEE Design and Test of Computers, 27, 6, 46-57, 2010-11-01
[ built-in self-repair , design and test , embedded memories , redundancy analysis , SoC , yield improvement ] -
DABISR: A defect-aware built-in self-repair scheme for single/multi-port RAMs in SoCs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 29, 10, 1628-1639, 2010-10-01
[ Built-in self-repair , built-in self-test , defect location , multi-port RAM , random access memory (RAM) ] -
Reliability-enhancement and self-repair schemes for SRAMs with static and dynamic faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 18, 9, 1361-1366, 2010-09-01
[ built-in self-repair , built-in self-test , dynamic faults , march test , Random access memories , reliability , static faults ] -
Testing comparison and delay faults of TCAMs with asymmetric cells
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 18, 6, 912-920, 2010-06-01
[ Asymmetric ternary content addressable memory (TCAM) cell , Comparison faults , Delay faults , March tests , Memory testing , TCAM ] -
ReBISR: A reconfigurable built-in self-repair scheme for random access memories in SOCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 18, 6, 921-932, 2010-06-01
[ Built-in redundancy analysis (BIRA) , Built-in self-repair (BISR) , Built-in self-test (BIST) , March test , Random access memory (RAM) , Yield improvement ] -
Testing random defect and process variation induced comparison faults of TCAMs with asymmetric cells
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 29, 11, 1843-1847, 2010-01-01
[ Comparison faults , content addressable memories , march tests , memory testing ] -
Memory built-in self test in multicore chips with mesh-based networks
IEEE Micro, 29, 5, 46-55, 2009-09-01
[ BIST , March test , Multicore , Network-on-chip , Random access memory , Testing. ] -
A built-in redundancy-analysis scheme for random access memories with two-level redundancy
Journal of Electronic Testing: Theory and Applications (JETTA), 24, 1-3, 181-192, 2008-06-01
[ Built-in redundancy-analysis (BIRA),Built-in self-repair (BISR),Random access memory,System-on-chip (SOC),Two-level redundancy ] -
A multi-code compression scheme for test time reduction of system-on-chip designs
IEICE Transactions on Information and Systems, E91-D, 10, 2428-2434, 2008-01-01
[ Compression , Decompression , Multi-code compression , System-on-chip , Test ] -
Raisin: Redundancy analysis algorithm simulation
IEEE Design and Test of Computers, 24, 4, 386-396, 2007-12-01
[ Algorithm simulation , BIRA , BISR , Raisin , Redundancy analysis , Repair rate , Yield ] -
ProTaR: An infrastructure IP for repairing RAMs in system-on-chips
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 15, 10, 1135-1143, 2007-10-01
[ Built-in self-repair (BISR) , Diagnosis , Infrastructure intelligent property (IIP) , Random access memories (RAMs) , System-on-chip (SOC) , Test ] -
Transparent-test methodologies for random access memories without/with ECC
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 26, 10, 1888-1893, 2007-10-01
[ Error-correction code (ECC) , March test , Random-access memory (RAM) , Reliability , Soft errors , Transparent test ] -
Testing ternary content addressable memories with active neighbourhood pattern-sensitive faults
IET Computers and Digital Techniques, 1, 3, 246-255, 2007-05-14 -
Testing ternary content addressable memories with comparison faults using march-like tests
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 26, 5, 919-931, 2007-05-01
[ Comparison faults , Content addressable memories (CAMs) , Delay faults , March tests , Memory testing , Ternary content addressable memories ] -
Testing ternary content addressable memories with comparison faults using march-like tests
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 26, 5, 919-931, 2007-05-01
[ Comparison faults , content addressable memories(CAMs) , delay faults , march tests , memory testing , ternarycontent addressable memories ] -
An efficient diagnosis scheme for RAMs with simple functional faults
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E90-A, 12, 2703-2711, 2007-01-01
[ Built-in selfdiagnosis , Coupling faults , Diagnosis , March test , Random access memories ] -
A built-in self-repair design for RAMs with 2-D redundancy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 13, 6, 742-745, 2005-06-01
[ Built-in redundancy analysis (BIRA) , Built-in self-repair (BISR) , Built-in self-test (BIST) , Embedded memories ] -
Efficient block-level connectivity verification algorithms for embedded memories
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E87-A, 12, 3185-3192, 2004-01-01
[ Embedded memories , Signal misplaced fault , System on chip , Verification ] -
Diagnosing Binary Content Addressable Memories with Comparison and RAM Faults
IEICE Transactions on Information and Systems, E87-D, 3, 601-608, 2004-01-01
[ Content addressable memories,Diagnosis,March test,Testing ] -
Built-In Redundancy Analysis for Memory Yield Improvement
IEEE Transactions on Reliability, 52, 4, 386-399, 2003-12-01
[ Built-in self-diagnosis , Built-in self-test , DRAM , Embedded memory , Memory testing , Redundancy analysis , SRAM , Yield improvement ] -
Testing and diagnosis methodologies for embedded content addressable memories
Journal of Electronic Testing: Theory and Applications (JETTA), 19, 2, 207-215, 2003-04-01
[ BIST , CAM , March test algorithm , Memory diagnostics , Memory testing ] -
A built-in self-test scheme with diagnostics support for embedded SRAM
Journal of Electronic Testing: Theory and Applications (JETTA), 18, 6, 637-647, 2002-12-01
[ Memory BIST , Memory diagnostics , Memory testing , RAM , Semiconductor memory ] -
A hierarchical test methodology for systems on chip
IEEE Micro, 22, 5, 69-81, 2002-09-01 -
Diagnostic data compression techniques for embedded memories with built-in self-test
Journal of Electronic Testing: Theory and Applications (JETTA), 18, 4-5, 515-527, 2002-08-01
[ Built-in self-test (BIST) , Data compression , Hamming syndrome , Huffman code , March test , Memory diagnostics , Memory testing , System-on-chip ] -
Efficient FFT network testing and diagnosis schemes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 10, 3, 267-277, 2002-06-01
[ Butterfly network , C-testable , Design-for-diagnosability , Design-for-testability , Diagnosis , Fa ult tolerance , Fast Fourier transform (FFT) , Logic testing , M-testable ] -
Core-based system-on-chip testing: Challenges and opportunities
Journal of the Chinese Institute of Electrical Engineering, Transactions of the Chinese Institute of Engineers, Series E/Chung KuoTien Chi Kung Chieng Hsueh K'an, 8, 4, 335-353, 2001-11-01
[ Built-in-self-test (BIST) , Core test language , IC testing , IEEE P1500 standard , System-on-chip (SOC) , Test scheduling ] -
Easily testable and fault-tolerant FFT butterfly networks
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 47, 9, 919-929, 2000-09-01
研討會著作
-
Effective design, modeling and testing techniques for digital computing-in memories with MAC function
2025-10-20
[ Computing in memories, test, transparent test, reliability ] -
Local trimming method for enhancing the read reliability of STT-MRAMs
2025-05-26
[ Trimming, STT-MRAM, BIST, reliability ] -
Behavioral model compiler for simulating read disturbances and read/write errors in STT-MRAMs
2025-04-21
[ STT-MRAM, behavior model, read/write disturbance ] -
A machine learning-based power prediction framework for DCIM circuits
2025-04-16
[ Power estimation, machine learning, digital computing-in memories ] -
Behavioral Model Compiler for Simulating Read Disturbances and Read/Write Errors in STT-MRAMs
2025-01-01
[ Behavioral Simulation,Design Automation,Memory Array,Memory Compiler,Reliability ] -
Local Trimming Method for Enhancing the Read Reliability of STT-MRAMs
2025-01-01
[ global trimming,local trimming,reference resistance,reliability,STT-MRAM,trimming ] -
Parallel-Check Trimming Test Approach for Selecting the Reference Resistance of STT-MRAMs
2024-01-01
[ built-in self-test,reference resistance,reliability,STT-MRAM,trimming,yield ] -
Efficient Built-In Self-Test Scheme for Inter-Die Interconnects of Chiplet-Based Chips
149-156, 2024-01-01
[ advanced packaging,built-in self-test,Chiplet,inter-die interconnect,interconnection testing ] -
Special Session: Testing of Digital Computing-In Memories with MAC Function
2024-01-01
[ Computing-in memories,fault analysis,March test,static random access memory,testing ] -
An on-line aging detection and tolerance framework for improving reliability of STT-MRAMs
2023-01-11
[ STT-MRAM, online, reliability, aging, computing in memory ] -
Fault-Aware ECC Scheme for Enhancing the Read Reliability of STT-MRAMs
2023-01-01
[ Error Correction Code,fault analysis,fault aware,reliability,STT-MRAM ] -
Hardware Trojans of Computing-In-Memories: Issues and Methods
2023-01-01
[ embedded memory,hardware security,integrated circuits,supply chain,Trojan mitigation ] -
Testing of Computing-In Memories: Faults, Test Algorithms, and Design-for-Testability
2023-01-01
[ Computing-in memory,design-for-testability,faults,test algorithm,testing ] -
Design and Dataflow for Multibit SRAM-Based MAC Operations
159-160, 2022-01-01
[ Computing-in-memory;multiply-and-accumulate,SRAMs ] -
Design and Test of Computing-In Memories
157-158, 2022-01-01
[ computing-in memory,MAC,test ] -
DFT-Enhanced Test Scheme for Spin-Transfer-Torque (STT) MRAMs
489-493, 2022-01-01
[ DFT,March test,STT MRAM,Test ] -
Foreword: ATS 2022
2022-01-01
-
Fault Modeling and Testing of RRAM-based Computing-In Memories
7-12, 2022-01-01
[ computing faults,computing-in memory,march test,Resistive RAM ] -
Testing and Reliability of Computing-In Memories: Solutions and Challenges
55-60, 2022-01-01
[ computing in memory,RAM,reliability,RRNM,STT-MRAM,test ] -
Evaluating the Impact of Fault-Tolerance Capability of Deep Neural Networks Caused by Faults
272-277, 2021-01-01
[ ] -
An Aging-Aware CMOS SRAM Structure Design for Boolean Logic In-Memory Computing
2021-01-01
[ 8T SRAM,In-Memory Computing,PBTI,supplemental transistor ] -
Testing of Configurable 8T SRAMs for In-Memory Computing
2020-11-23
[ content addressable memory,In-memory computing,March-like test,static random access memory,testing ] -
Refresh Power Reduction of DRAMs in DNN Systems Using Hybrid Voting and ECC Method
41-46, 2020-09-01
[ Deep neural network,dynamic random access memory,error-correction code,low power ] -
Testing of in-memory-computing 8T SRAMs
2019-10-01
[ ] -
3D Test Wrapper Chain Optimization with I/O Cells Binding Considered
2019-10-01
[ Optimization Algorithm,Test Time,Test TSV,Test Wrapper Chain Synthesis,TSV Count ] -
A Built-in Self-Test Scheme for TSVs of Logic-DRAM Stacked 3D ICs
2019-10-01
[ 3D IC,built-in self-Test,DRAM die,TSV ] -
Configurable 8T SRAM for Enbling in-Memory Computing
112-116, 2019-04-01
[ computing architecture,content addressable memory,static random access memory ] -
Diagnosis of Resistive Nonvolatile-8T SRAMs
23-24, 2019-02-22
[ Diagnosis,March test,Memristor,Nonvolatile SRAM ] -
Testing stuck-open faults of priority address encoder in content addressable memories
382-387, 2019-01-21
[ Comparison faults,Content addressable memories,Memory testing,Priority encoder faults ] -
Modeling and testing comparison faults of memristive ternary content addressable memories
1-6, 2018-06-29
[ ] -
A channel-sharable built-in self-test scheme for multi-channel DRAMs
245-250, 2018-02-20
[ built-in self-test,channel-based DRAM,DRAM,March test,test ] -
Foreword: 26th IEEE Asian test symposium (ATS 2017)
2018-01-24
-
Software-hardware-cooperated built-in self-test scheme for channel-based DRAMs
107-111, 2017-11-03
[ built-in self-test,channel-based DRAM,DRAM,processor,test ] -
A built-in self-Test scheme for classifying refresh periods of DRAMs
2017-07-03
[ ] -
A Test Method for Finding Boundary Currents of 1T1R Memristor Memories
281-286, 2016-12-22
[ Memristor,non-volatile memory,process variation,reliability,test ] -
A built-in method for measuring the delay of TSVs in 3D ICs
2016-07-22
[ ] -
A built-in self-repair scheme for DRAMs with spare rows, columns, and bits
2016-07-02
[ built-in self-repair,built-in self-Test,DRAM,redundancy,redundancy analysis ] -
Fault modeling and testing of resistive nonvolatile-8T SRAMs
2016-05-23
[ fault model,March test,Memristor,nonvolatile SRAM,test algorithm ] -
A hybrid built-in self-test scheme for DRAMs
2015-05-28
[ ] -
Testing Inter-Word Coupling Faults of Wide I/O DRAMs
67-72, 2015-02-28
[ burst length,coupling faults,DRAM,fault coverage,March test ] -
Fault modeling and testing of 1T1R memristor memories
2015-01-01
[ memristor,Non-volatile memory,resistive memory,test ] -
Yield-enhancement schemes for multicore processor and memory stacked 3D ICs
2014-03-01
[ Algorithms,B.8.1 [performance and reliability]: reliability, testing, and fault toelerance,Design,Reliability ] -
BIST-assisted tuning scheme for minimizing io-channel power of TSV-based 3D DRAMs
1-6, 2014-01-01
[ 3D IC,at-speed test,BIST,DRAM,low power,through silicon via ] -
Testing of non-volatile logic-based system chips
224-229, 2014-01-01
[ ] -
Intra-channel reconfigurable interface for TSV and micro bump fault tolerance in 3-d RAMs
143-148, 2014-01-01
[ 3-D IC,DRAM,fault tolerance,interface,TSV,yield enhancement ] -
An FPGA-based test platform for analyzing data retention time distribution of DRAMs
2013-08-15
[ ] -
Allocation of RAM built-in self-repair circuits for SOC dies of 3D ICs
2013-08-14
[ ] -
A hybrid ECC and redundancy technique for reducing refresh power of DRAMs
2013-08-14
[ ] -
A TSV repair scheme using enhanced test access architecture for 3-D ICs
7-12, 2013-01-01
[ ] -
Testing disturbance faults in various NAND flash memories
221-226, 2013-01-01
[ ] -
A built-in self-test scheme for 3D RAMs
2012-12-01
[ 3D Random Acces Memory,built-in self-test,March test,through-silicon-via ] -
Test cost optimization technique for the pre-bond test of 3D ICs
102-107, 2012-08-20
[ ] -
Disturbance fault testing on various NAND flash memories
2012-08-13
[ ] -
Area and reliability efficient ECC scheme for 3D RAMs
2012-07-25
[ ] -
Post-bond test techniques for TSVs with crosstalk faults in 3D ICs
2012-07-25
[ ] -
On test and repair of 3D random access memory
744-749, 2012-04-26
[ ] -
A built-in self-test scheme for the post-bond test of TSVs in 3D ICs
20-25, 2011-07-01
[ ] -
Built-in self-diagnosis and test time reduction techniques for NAND flash memories
260-263, 2011-06-28
[ ] -
A built-in redundancy-analysis scheme for RAMs with 3D redundancy
264-267, 2011-06-28
[ ] -
Enhanced IEEE 1500 test wrapper for testing small RAMs in SOCs
236-240, 2010-12-01
[ ] -
A test integration methodology for 3D integrated circuits
377-382, 2010-12-01
[ ] -
Yield-enhancement techniques for 3D random access memories
104-107, 2010-11-08
[ ] -
A low-cost and scalable test architecture for multi-core chips
30-35, 2010-11-03
[ Array testing,Diagnosis,Multi-core,Scalable test architecture,Test,Test access mechanism ] -
A low-cost Built-in Self-Test scheme for an array of memories
75-80, 2010-11-03
[ ] -
Automatic generation of memory built-in self-repair circuits in SOCs for minimizing test time and area cost
21-26, 2010-06-29
[ ] -
Test and repair scheduling for built-in self-repair RAMs in SOCs
3-7, 2010-05-21
[ ] -
Is 3D integration an opportunity or just a hype?
541-543, 2010-04-28
[ ] -
3-D content addressable memory architectures
59-64, 2009-12-25
[ ] -
Variability-tolerant binary content addressable memory cells
44-49, 2009-12-25
[ ] -
A built-in self-repair method for RAMs in mesh-based NoCs
259-262, 2009-12-01
-
Testability exploration of 3-D RAMs and CAMs
397-402, 2009-12-01
[ ] -
Modeling and testing comparison faults of TCAMs with asymmetric cells
15-20, 2009-11-02
-
A programmable online/off-line built-in self-test scheme for RAMs with ECC
1997-2000, 2009-10-26
-
Diagnosis algorithms for locating bridge defects in multi-port RAMs
2009-09-17
-
Efficient diagnosis algorithms for drowsy SRAMs
276-279, 2009-07-08
-
A low-cost pipelined BIST scheme for homogeneous RAMs in multicore chips
357-362, 2008-12-01
-
A Shared Parallel Built-In Self-Repair Scheme for Random Access Memories in SOCs
2008-12-01
-
CAMEL: An efficient fault simulator with coupling fault simulation enhancement for CAMs
355-360, 2007-12-01
-
Testing comparison faults of ternary content addressable memories with asymmetric cells
501-506, 2007-12-01
-
Diagnosing scan chains using SAT-based diagnostic pattern generation
273-276, 2007-12-01
-
Design of cost-efficient memory-based FFT processors using single-port memories
29-32, 2007-12-01
-
A built-in self-repair scheme for multiport RAMs
355-360, 2007-12-01
-
An infrastructure IP for repairing multiple RAMs in SOCs
163-166, 2007-10-01
-
A multi-code compression technique for reducing system-on-chip test time
239-242, 2007-10-01
-
Testing crosstalk faults of data and address buses in embedded RAMs
2007-09-28
-
Testing active neighborhood pattern-sensitive faults of ternary content addressable memories
55-60, 2006-12-15
-
Verification methodology for self-repairable memory systems
109-114, 2006-12-01
-
A built-in redundancy-analysis scheme for RAMs with 2D redundancy using ID local bitmap
2006-12-01
-
A built-in redundancy-analysis scheme for self-repairable RAMs with two-level redundancy
362-370, 2006-12-01
-
A reconfigurable built-in self-repair scheme for multiple repairable RAMs in SOCs
2006-01-01
[ Built-in redundancy-analysis , Built-in self-repair , March test , RAMs , Reconfigurable , Redundancy , SOCs ] -
An error detection and correction scheme for RAMs with partial-write function
115-120, 2005-12-09
-
An efficient transparent test scheme for embedded word-oriented memories
574-579, 2005-12-01
-
Modeling and Testing comparison faults for ternary content addressable memories
60-65, 2005-12-01
-
Testing priority address encoder faults of content addressable memories
826-833, 2005-12-01
[ Comparison faults , Content addressable memories , Priority address encoder faults ] -
Testing comparison faults of ternary CAMs based on comparison faults of binary CAMs
65-70, 2005-01-01
-
A design methodology for hybrid carry-lookahead/carry-select adders with reconfigurability
77-80, 2005-01-01
-
Design of reconfigurable array multipliers and multiplier-accumulators
37-40, 2004-12-01
-
Efficient testing methodologies for conditional sum adders
319-324, 2004-12-01
-
An efficient diagnosis scheme for random access memories
277-282, 2004-12-01
-
Design of reconfigurable carry select adders
825-828, 2004-12-01
-
A Built-in Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy
393-402, 2003-11-06
[ Built-in redundancy-analysis , Built-in self-repair , Built-in self-test , Memory testing , Semiconductor memory ] -
A testability-driven optimizer and wrapper generator for embedded memories
53-56, 2003-01-01
-
A hierarchical test scheme for system-on-chip designs
486-490, 2002-12-01
-
Testing and diagnosing embedded content addressable memories
389-394, 2002-01-01
[ Associative memory , CADCAM , Cams , Circuit faults , Circuit testing , Computer aided manufacturing , Coupling circuits , Electrical fault detection , Impedance matching , Random access memory ] -
A simulator for evaluating redundancy analysis algorithms of repairable embedded memories
68-73, 2002-01-01
[ Algorithm design and analysis , Analytical models , Built-in self-test , Circuit faults , Circuit simulation , Circuit testing , Computational modeling , Electrical fault detection , Fault detection , Redundancy ] -
A simulator for evaluating redundancy analysis algorithms of repairable embedded memories
262-267, 2002-01-01
[ embedded memory , memory repair , memory testing , redundancy analysis , simulation ] -
March-based RAM diagnosis algorithms for stuck-at and coupling faults
758-767, 2001-12-01
-
Memory fault diagnosis by syndrome compression
97-101, 2001-12-01
-
Using syndrome compression for memory built-in self-diagnosis
303-306, 2001-01-01
-
Built-in self-test and self-diagnosis scheme for embedded SRAM
45-50, 2000-12-01
-
Testable and fault tolerant design for FFT networks
201-209, 1999-12-01
-
Testable and fault tolerant design for FFT networks
201-209, 1999-01-01
校外榮譽
- 111 [史丹佛大學] 史丹福大學公布 - 2022全球前2%頂尖科學家(終身影響力)
- 110 [史丹佛大學] 史丹福大學公布 - 2021全球前2%頂尖科學家(終身影響力)
- 104 [中國電機工程學會] 中國電機工程師學會(CIEE)傑出電機工程教授獎
- 81 [科技部] 傑出研究獎
校內獲獎
- 115 研究傑出獎
- 113 研究傑出獎
- 112 研究傑出獎
- 111 研究傑出獎
- 108 特聘教授
- 107 研究傑出獎
- 106 研究傑出獎
- 105 研究傑出獎
期刊編輯
-
114 ~ 114
IEEE Design and Test
ISSN 2168-2356 EISSN 2168-2364
編輯委員 -
113 ~ 113
IEEE Design and Test
ISSN 2155-5044 EISSN 2155-5052
期刊編輯委員 -
112 ~ 112
IEEE Design and Test
ISSN 2168-2356 EISSN 2168-2364
編輯委員 -
111 ~ 111
IEEE Design and Test
ISSN 2168-2356 EISSN 2168-2364
期刊編輯委員 -
110 ~ 110
IEEE Design and Test
ISSN 2168-2356 EISSN 2168-2364
期刊編輯委員 -
110 ~ 110
IEEE Design and Test
ISSN 2168-2356 EISSN 2168-2364
期刊編輯委員 -
109 ~ 109
IEEE Design and Test
ISSN 2168-2356 EISSN 2168-2364
期刊編輯委員 -
108 ~ 108
IEEE Design and Test
ISSN 2168-2356 EISSN 2168-2364
擔任期刊編輯委員 -
107 ~ 107
IEEE Design and Test
ISSN 2168-2356 EISSN 2168-2364
期刊編輯委員
- 記憶體裝置參考電阻修整方法與記憶體裝置 [中華民國]
- 用於自旋轉移矩磁阻式隨機存取記憶體之糾錯系統及糾錯方法 [中華民國]
- 延遲量測電路及其量測方法 DELAY MEASUREMENT CIRCUIT AND MEASURING METHOD THEREOF [美國]
- 延遲量測電路及其量測方法 DELAY MEASUREMENT CIRCUIT AND MEASURING METHOD THEREOF [中華民國]
- 應用於記憶體陣列的參考電阻設定之平行檢測修剪測試方法 [中華民國]
國立中央大學