國立中央大學教師履歷平台

期刊著作

• Filamentary Random Telegraph Noise-Based Multiple-Resistive-State True Random Number Generator for Probabilistic Hot/Cold Bits
  IEEE Transactions on Electron Devices, 72, 7, 3573-3581, 2025-01-01
  [ Probabilistic computing-in-memory,random access memory (RRAM),random telegraph noise (RTN),true random number generators (TRNGs) ]

• A Nonvolatile Ternary-Content-Addressable- Memory Comprising Resistive-Gate Field-Effect Transistors
  IEEE Electron Device Letters, 44, 8, 1292-1295, 2023-08-01
  [ in-memory-searching,Nonvolatile ternary-content-addressable-memory (nv-TCAM),resistive-gate field-effect-transistor (RG-FET) ]

• 1-Transistor 1-Source/Channel/Drain-Diode (1T1D) One-Time-Programmable Memory in 14-nm FinFET
  IEEE Electron Device Letters, 44, 3, 404-407, 2023-03-01
  [ avalanche-breakdown,embedded memory,impact-ionization,One-time-programmable (OTP) memory ]

• A Logic Fully Comparable Single-Supply Capacitor-Less 1-FinFET-1-Source-Channel-Drain-Diode (1T1D) Embedded DRAM MACRO in 16-nm FinFET
  IEEE Solid-State Circuits Letters, 6, 249-252, 2023-01-01
  [ Dynamic-random-access-memory,embedded-memory,fin-type-field-effect-transistor (FinFET) ]

• Emulator of Gene Mutation: Interfering True Random Number Generators Using Resistive-Gate Non-Volatile-Memories
  IEEE Electron Device Letters, 43, 11, 1870-1873, 2022-11-01
  [ gene mutation,Resistive-gate non-volatile-memory,true random number generator ]

• Positive-Bias-Temperature-Instability Induced Random-Trap-Fluctuation Enhanced Physical Unclonable Functions on 14-nm nFinFETs
  IEEE Electron Device Letters, 43, 9, 1396-1399, 2022-09-01
  [ physical unclonable function,positive-bias-temperature-instability,Random trap fluctuation ]

• Cryogenic Quasi-Ballistic Transport Enhanced by Strained Silicon Technologies in 14-nm Complementary Fin Field Effect Transistors Through Virtual Source Model
  IEEE Transactions on Electron Devices, 2022-01-01

• A three-bit-per-cell via-type resistive random access memory gated metal-oxide semiconductor field-effect transistor non-volatile memory with the FORMing-free characteristic
  Semiconductor Science and Technology, 36, 12, 2021-12-01

• Oxygen diffusion barrier on interfacial layer formed with remote NH3 plasma treatment
  Surface and Coatings Technology, 423, 2021-10-15
  [ Alloy-like Interface,Ge nMOSFET,Interfacial layer,Oxidation state,Oxygen diffusion barrier,Remote plasma treatment ]

• An embedded three-bit-per-cell two-transistors and one-ferroelectric-capacitance nonvolatile memory
  IEEE Electron Device Letters, 42, 10, 1460-1463, 2021-10-01

• RADAR: A Fast and Energy-Efficient Programming Technique for Multiple Bits-Per-Cell RRAM Arrays
  IEEE Transactions on Electron Devices, 68, 9, 4397-4403, 2021-09-01
  [ Energy-efficient memory,HfO2resistive RAM (RRAM),multiple bits-per-cell RRAM,nonvolatile memory,RRAM programming ]

• A FORMing-Free HfO2-/HfON-Based Resistive-Gate Metal-Oxide-Semiconductor Field-Effect-Transistor (RG-MOSFET) Nonvolatile Memory with 3-Bit-Per-Cell Storage Capability
  IEEE Transactions on Electron Devices, 68, 6, 2699-2704, 2021-06-01
  [ Flash memory cells,nonvolatile memory (NVM),resistive random access memory (RAM),resistive-gate metal-oxide-semiconductor-field-effect transistor (RG-MOSFET) ]

• Four-Bits-Per-Memory One-Transistor-and-Eight-Resistive-Random-Access-Memory (1T8R) Array
  IEEE Electron Device Letters, 42, 3, 335-338, 2021-03-01
  [ 1T8R,4-bits-per-RRAM,gradual-SET/RESET,RRAM ]

• An Experimental Approach to Characterizing the Channel Local Temperature Induced by Self-Heating Effect in FinFET
  IEEE Journal of the Electron Devices Society, 6, 866-874, 2018-07-23
  [ FinFET,random telegraph noise,self-heating effect ]

• A 14-nm FinFET Logic CMOS Process Compatible RRAM Flash with Excellent Immunity to Sneak Path
  IEEE Transactions on Electron Devices, 64, 12, 4910-4918, 2017-12-01
  [ Embedded memory,FinFET,high-k metal gate,Moore's gap,RRAM,sneak path ]

• A theoretical and experimental evaluation of surface roughness variation in trigate metal oxide semiconductor field effect transistors
  Journal of Applied Physics, 119, 20, 2016-05-28

• The understanding on the evolution of stress-induced gate leakage in high-k dielectric metal-oxide-field-effect transistor by random-telegraph-noise measurement
  Applied Physics Letters, 107, 24, 2015-12-14

• The understanding of the drain-current fluctuation in a silicon-carbon source-drain strained n-channel metal-oxide-semiconductor field-effect transistors
  Applied Physics Letters, 104, 20, 2014-05-19

• The mechanisms of random trap fluctuation in metal oxide semiconductor field effect transistors
  Applied Physics Letters, 101, 22, 2012-11-26

• Suppressing device variability by cryogenic implant for 28-nm low-power SoC applications
  IEEE Electron Device Letters, 33, 10, 1444-1446, 2012-01-01
  [ Cryogenic implant,ion implantation,logic device,novel process technology,random dopant fluctuation ]

• The proximity of the strain induced effect to improve the electron mobility in a silicon-carbon source-drain structure of n-channel metal-oxide- semiconductor field-effect transistors
  Applied Physics Letters, 96, 9, 2010-03-19

研討會著作

• 4.6-bits-per-cell Resistive Probabilistic-bit Computing for High-efficient Evaluation of Bio-Genomic Evolution Achieving 6.25x Acceleration of Data-operations
  2025-01-01
  

• InAs/AlSb III-V NVM with High-Speed (5ns) Low-Power (1V) QW-Tunnel Program for 10-Year Storage by 2DEG-Enhanced Retention
  32-33, 2025-01-01
  [ 2DEG,III-V NVM,InAs/AlSb,Quantum-tunnel ]

• Below 10A CMOS- Double CFETs (c-FETs) with Dielectric-Wall-Stress by Isolation-Last Process for 0.0069 um2 of SRAM-Cell Design
  22-23, 2025-01-01
  [ (Greek text)c-FETs,6T SRAM,D-FF,Dielectric-wall ]

• Experimental Characterization of Dopant Freeze-out Effect Enhanced Electrical Variability in Cryogenic 16-nm Complementary FinFETs
  2025-01-01
  

• Ultra-scale (0.014 μm2) High-efficient 10A 6T CFET-SRAM Cells Combined Backside Power Deliver Networks and Backside Bit-lines
  2025-01-01
  [ 10A CFETs,BPDN,SRAM ]

• A New 1C1T1R nv-TCAM with Simultaneously Hybrid Ferroelectricity and Memristor Layers Feasible for Ultra-highly-dense and High-performance In-memory-searching
  2024-01-01
  [ ferro-electricity,in-memory-searching,memristor,nv-TCAM,RRAM ]

• A New Design of Ultra-Scaled and High-Density 1-nm Node 6T-SRAM Cell by Lateral-and-Complementary FETs (LC-FETs) with only 21 F2
  2024-01-01
  [ CFET,LFET,Nanosheet MOSFET,SRAM ]

• Design of the 2-nm Nanosheet NAND-type TCAM with High Speed and Compat Cell-size: 45% Layout-reduction of 3-nm TCAM
  119-120, 2024-01-01
  [ 2-nm CMOS Devices,FinFETs,Nanosheet,SRAM ]

• A Novel RRAM-based Ternary Strong-PUF with High Security Intensity Feasible for Low-earth Orbit Satellites in the 6G Era
  23-24, 2024-01-01
  

• A 40-nm Loadless 4T-SRAM TRNG MACRO with Read-just-after-write (RAW) Scheme Featuring 5.3Gb/s and 3.64TOP/W
  111-112, 2023-01-01
  

• 3-bits-per-cell 2T32CFEnvTCAM by Angstrom-laminated Ferroelectric Layers with 1011Cycles of Endurance and 4.92V of Ultra-wide Memory-windows for In-memory-searching
  2023-01-01
  

• A Built-in Spice Time-domain Variation Model of the BTI-induced Random Trap Fluctuation (RTF) in 14 nm FinFETs
  2022-01-01
  

• NVDimm-FE: A High-density 3D Architecture of 3-bit/c 2TnCFEto Break Great Memory Wall with 10 ns of PGM-pulse, 1010Cycles of Endurance, and Decade Lifetime at 103 °C
  359-360, 2022-01-01
  

• The Extension of the FinFET Generation Towards Sub-3nm: The Strategy and Guidelines
  15-17, 2022-01-01
  

• A Novel Physical Unclonable Function: NBTI-PUF Realized by Random Trap Fluctuation (RTF) Enhanced True Randomness in 14 nm FinFET Platform
  2022-01-01
  

• FinFET Plus: A scalable FinFET architecture with 3D air-gap and air-spacer toward the 3nm generation and beyond
  2021-04-19
  

• A Reliable Triple-Level Operation of Resistive-Gate Flash Featuring Forming-Free and High Immunity to Sneak Path
  2021-03-01
  

• The First Embedded 14nm FeFinFET NVM: 2T1CFE Array as Electrical Synapses and Activations for High-performance and Low-power Inference Accelerators
  2021-01-01
  

• Fin-TFET: Design of FinFET-based Tunneling FET with Face-tunneling Mechanism
  2021-01-01
  

• Novel concept of hardware security in using gate-switching FinFET nonvolatile memory to implement true-random-number generator
  39.3.1-39.3.4, 2020-12-12
  

• A novel complementary architecture of one-time-programmable memory and its applications as physical unclonable function (PUF) and one-time password
  31.6.1-31.6.4, 2020-12-12
  

• Design of Low Voltage Vertical Channel Face-tunneling TFET Using Ge/SiGe Materials and Its SRAM Circuit Performance
  132-133, 2020-08-01
  

• A Self-align Gate-last Resistive Gate Switching FinFET Nonvolatile Memory Feasible for Embedded Applications
  23-24, 2020-06-01
  

• A Pulsed RTN Transient Measurement Technique: Demonstration on the Understanding of the Switching in Resistance Memory
  2020-04-01
  [ Oxygen-vacancy-based RAM,Resistance memory,RTN,RTN transient measurement,Soft-breakdown ]

• High-Density Multiple Bits-per-Cell 1T4R RRAM Array with Gradual SET/RESET and its Effectiveness for Deep Learning
  2019-12-01
  

• Novel Concept of the Transistor Variation Directed Toward the Circuit Implementation of Physical Unclonable Function (PUF) and True-random-number Generator (TRNG)
  2019-12-01
  

• The Demonstration of Gate Dielectric-fuse 4kb OTP Memory Feasible for Embedded Applications in High-k Metal-gate CMOS Generations and beyond
  C208-C209, 2019-06-01
  

• The understanding of gate capacitance matching on achieving a high performance NC MOSFET with sufficient mobility
  2019-06-01
  

• A Novel Architecture to Build Ideal-linearity Neuromorphic Synapses on a Pure Logic FinFET Platform Featuring 2.5ns PGM-time and 1012 Endurance
  T138-T139, 2019-06-01
  

• Embedded PUF on 14nm HKMG FinFET Platform: A Novel 2-bit-per-cell OTP-based Memory Feasible for IoT Secuirty Solution in 5G Era
  T118-T119, 2019-06-01
  

• The guideline on designing a high performance nc mosfet by matching the gate capacitance and mobility enhancement
  2019-04-01
  

• An energy efficient FinFET-based Field Programmable Synapse Array (FPSA) feasible for one-shot learning on EDGE AI
  29-30, 2018-10-25
  

• The Design of High Performance Si/SiGe-Based Tunneling FET: Strategies and Solutions
  2018-10-09
  

• A Novel Approach to Localize the Channel Temperature Induced by the Self-heating Effect in 14nm High-k Metal-gate FinFET
  148-150, 2018-07-26
  

• A novel rewritable one-time-programming OTP (RW-OTP) realized by dielectric-fuse RRAM devices featuring ultra-high reliable retention and good endurance for embedded applications
  1-2, 2018-07-03
  

• The guideline on designing face-tunneling FET for large-scale-device applications in IoT
  3-4, 2017-12-29
  

• The impact of TiN barrier on the NBTI in an advanced high-k metal-gate p-channel MOSFET
  1-4, 2017-10-05
  

• The issues on the power consumption of Trigate FinFET: The design and manufacturing guidelines
  1-4, 2017-10-05
  

• First demonstration of flash RRAM on pure CMOS logic 14nm FinFET platform featuring excellent immunity to sneak-path and MLC capability
  T72-T73, 2017-07-31
  

• Geometric variation: A novel approach to examine the surface roughness and the line roughness effects in trigate FinFETs
  130-131, 2017-06-13
  

• A novel design of P-N staggered face-tunneling TFET targeting for low power and appropriate performance applications
  2017-06-07
  

• A novel one transistor non-volatile memory feasible for NOR and NAND applications in IoT era
  44-45, 2016-09-27
  

• A new variation plot to examine the interfacial-dipole induced work-function variation in advanced high-k metal-gate CMOS devices
  2016-09-21
  

• Experimental techniques on the understanding of the charge loss in a SONOS nitride-storage nonvolatile memory
  38-42, 2016-09-09
  [ charge loss,endurance,gated-diode measurement,Random Telegraph Noise (RTN),retention,SONOS flash memory ]

• A novel one transistor resistance-gate nonvolatile memory
  2016-08-22
  

• An Innovative 1T1R Dipole Dynamic Random Access Memory (DiRAM) featuring high speed, ultra-low power, and low voltage operation
  2016-05-27
  

• A comprehensive transport model for high performance HEMTs considering the parasitic resistance and capacitance effects
  152-153, 2015-12-04
  

• Design of complementary tilt-gate TFETs with SiGe/Si and III-V integrations feasible for ultra-low-power applications
  2015-09-24
  [ CMOS integrated circuits,Electric fields,Logic gates,Random access memory,Silicon,Silicon germanium,Tunneling ]

• The RTN measurement technique on leakage path finding in advanced high-k metal gate CMOS devices
  154-157, 2015-08-25
  

• A circuit level variability prediction of basic logic gates in advanced trigate CMOS technology
  12.2.1-12.2.4, 2015-02-20
  

• The demonstration of low-cost and logic process fully-compatible OTP memory on advanced HKMG CMOS with a newly found dielectric fuse breakdown
  3.4.1-3.4.4, 2015-02-16
  

• The experimental demonstration of the BTI-induced breakdown path in 28nm high-k metal gate technology CMOS devices
  2014-01-01
  

• The observation of BTI-induced RTN traps in inversion and accumulation modes on HfO2 high-k metal gate 28nm CMOS devices
  2014-01-01
  

• Gate current variation: A new theory and practice on investigating the off-state leakage of trigate MOSFETs and the power dissipation of SRAM
  2013-12-01
  

• The understanding of the bulk trigate MOSFET's reliability through the manipulation of RTN traps
  2013-08-12
  

• The understanding of multi-level RTN in trigate MOSFETs through the 2D profiling of traps and its impact on SRAM performance: A new failure mechanism found
  2012-12-01
  

• The impact of the carrier transport on the random dopant induced drain current variation in the saturation regime of advanced strained-silicon CMOS devices
  2012-10-12
  

• The understanding of the trap induced variation in bulk tri-gate devices by a novel Random Trap Profiling (RTP) technique
  189-190, 2012-09-27
  

• New criteria for the RDF induced drain current variation considering strain and transport effects in strain-silicon CMOS devices
  2012-07-16
  

• A novel and direct experimental observation of the discrete dopant effect in ultra-scaled CMOS devices
  194-195, 2011-09-16
  

• Experimental determination of the transport parameters in high performance Dopant-Segregated Schottky-barrier MOSFETs
  120-121, 2011-07-11
  

• New observations on the physical mechanism of Vth-variation in nanoscale CMOS devices after long term stress
  2011-06-23
  [ hot carrier effect,random dopant fluctuation,random trap fluctuation ]

• A new type of inverter with juctionless (J-Less) transistors
  2010-10-22
  

• The investigation of the stress-induced traps and its correlation to PBTI in high-k dielectrics nMOSFETs by the RTN measurement technique
  70-71, 2010-10-20
  [ High-k (HfSiON) dielectrics nMOSFETs,Positive bias temperature instability (PBTI),Random telegraph noise (RTN) ]

• The understanding of strain-induced device degradation in advanced MOSFETs with process-induced strain technology of 65nm node and beyond
  1053-1054, 2010-10-20
  [ MOSFET,Random Telegraph Noise,Strained-silicon ]

• A new and simple experimental approach to characterizing the carrier transport and reliability of strained CMOS devices in the quasi-ballistic regime
  2009-12-01
  

• Design of high-performance and highly reliable nMOSFETs with embedded Si:C S/D extension stressor(Si:C S/D-E)
  158-159, 2009-11-16
  [ CMOS,Embedded SiC,Positive temperature bias instability,Strained technology ]

• A new observation of strain-induced slow traps in advanced CMOS technology with process-induced strain using random telegraph noise measurement
  52-53, 2009-11-16
  [ Random telegraph noise,Slow trap,Strained-Si devices ]

• More strain and less stress- The guideline for developing high-end strained CMOS technologie s with acceptable reliability
  2008-12-01
  

• New observation of an abnormal leakage current in advanced CMOS devices with short channel lengths down to 50nm and beyond
  2008-12-01
  

• The ballistic transport and reliability of the SOI and strained-SOI nMOSFETs with 65nm node and beyond technology
  120-121, 2008-08-14
  

專書

• Noise in Nanoscale Semiconductor Devices
  175-200, 2020-04-26